Control system for high speed printers



Nov. 2, 1965 1.. w. MARSH, JR

CONTROL SYSTEM FOR HIGH SPEED PRINTERS 5 Sheets-Sheet 1 Filed March 8,1962 INVENTOR.

LYNN W. MAR SH ATTORNEYS Nov. 2, 1965 w. MARSH, JR

CONTROL SYSTEM FOR HIGH SPEED PRINTERS 5 Sheets-Sheet 2 Filed March 8,1962 5 Sheets-Sheet 3 Nov. 2, 1965 w. MARSH, JR

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CONTROL SYSTEM FOR HIGH SPEED PRINTERS 5 Sheets-Sheet 5 Filed March 8,1962 Ilill h h S Q m H W U w E 1 M 25% E r 55:8 mm W l h N mm N 1 mv Y uL a 2 M Y Al E5 x I B 1 It 4.13.1 S 2 v OZEZMO F 3 r @o Ea 553210 a p owE0 2 ,2 1 A, 26E 2 E v v Nil .f Y u mm $2523 F M $.51 In 59/: .6128 M555muse/E1 United States Patent 0 3,215,985 CONTROL SYSTEM FOR HIGH SPEEDPRINTERS Lynn W. Marsh, Jr., Marblehead, Mass, assignor to AnelexCorporation, Boston, Mass, a corporation of New Hampshire Filed Mar. 8,1962, Ser. No. 178,445 5 Claims. (Cl. 340172.5)

My invention relates to high speed printers, and particularly to animproved system for actuating the print hammers of a high speed printerin response to data representing the characters of a line to be printed.

Various high speed printers have been devised for printing a line ofcharacters stored in the form of a selected code. For example, onewidely used printer comprises a series of constantly rotating printrolls, one for each column in the line to be printed. Each print rollhas a font of characters formed on its periphery, and each cooperateswith a print hammer which, when actuated,

strikes a record sheet and a transfer sheet against the print roll torecord the character then in position on the record sheet. In order toactuate each hammer when the character in printing position on theassociated print roll corresponds to the stored character, it isnecessary to compare each character, as it comes into position, with thestored character. United States Letters Patent No. 2,805,620, issuedSeptember 10, 1957 to Leo Rosen, Howard C. Barlow and Ray L. Bowman forControl Means For High Speed Printing Apparatus, for example, showsvarious ways in which such a comparison may be made. t

Prior to my invention, the apparatus required to make comparisons foreach character has been extremely complex, particularly in printers inwhich as many as one hundred and twenty columns per line are provided. Aprimary object of my invention is to reduce the amount and complexity ofthe apparatus required to make the character comparisons in a high speedprinter.

Briefly, the control system of my invention comprises a novel orderedsequence comparator in which a code generated in a predeterminedsequence is compared with the code representing each character for aline to be printed, not bitby-bit as in former comparators, but in termsof predetermined code sets, such that each generated code sequence isregistered as the same as any character code in the same set. Ambiguityis prevented by selecting the order in which the comparison sequence isgenerated, and by the provision of a novel final detection circuitcapable of responding only once during each comparison sequence. As willappear, the control system of my invention may be adapted for use eitherin systems in which input character codes are available throughout theprinting of a line, or in systems in which character codes are presentedonly transiently, one after another until a complete line has beenstored.

My invention will best be understood by reference to the accompanyingdrawings, together with the following detailed description.

In the drawings,

FIGS. la and 1b, when arranged horizontally side by side with FIG. 1::at the left, comprise a schematic wiring diagram of a print controlsystem, for high speed printers in which data representing a line ofcharacters is available throughout the printing of the line, inaccordance with one embodiment of my invention;

FIG. 2 is a schematic wiring diagram showing the internal details of thecomparators, print hammer drivers, and the hammer drive control unitshown in block diagram form in FIG 1; and

FIGS. 3a and 3b, when arranged horizontally side by side with FIG. 3a atthe left, comprise a schematic wiring diagram of a print control system,for printers in which the data for each character to be printed isavailable Patented Nov. 2, 1965 "ice transiently, in accordance with asecond embodiment of my invention.

In the drawings, certain conventions have been adopted to facilitate aconcise explanation of my invention. Conventional elements, such aslogical gates, bistable multivibrators, and delay lines, have been shownin block diagram form. Units requiring detailed description, which areduplicated in the system, are shown in circuit detail at least once,within a dotted rectangle arbitrarily provided with external referenceterminals, and similarly designated blocks having the same referenceterminals elsewhere in the system are to be assumed to be of the sameinternal construction. The various components of the system are arrangedon the drawings in an order selected to illustrate their functions inthe system; in practice, the components would be arranged in the mannerdictated by conventional wiring practice.

Referring now to FIG. 1, the first embodiment of my invention to bedescribed is shown adapted to control a conventional printer of the typecomprising a constantly rotating array of print wheels 1, mounted on ashaft 2 connected to the output shaft of a constant speed motor M forrotation in the sense shown by the curved arrows. As schematicallyindicated, any selected number of print wheels 1 may be provided, eachcorresponding to a character column in a line to be printed. Thus, thefirst print wheel Pl may be be separated from the last print wheel Pn byany selected number of intermediate print wheels. Each print wheel suchas P1 is engraved or otherwise formed with indicia comprising acharacter font around its periphery, and is associated with a printhammer such as H1, which is pivoted from a suitable support, not shown,and restrained by a suitable spring such as HSI. In response to theenergization of a hammer coil such as HCl, provided for each printhammer, the print hammer such as H1 strikes against a record sheet and atransfer ribbon, not shown, which are fed between the hammers and theprint wheels, to record the character then adjacent the hammer on therecord sheet. Since this apparatus is well known in the art, it will notbe described in detail; a fuller description may be found in US. PatentNo. 2,805,620, referred to above. It should be noted in this regard thatthe details of the printer do not form a part of, nor are they essentialto, my invention; it is only necessary in the illustrated embodimentthat the characters in a font for each column be available for printingin a fixed time sequence, and any printer in which such a sequence isenforced may readily be adapted to the apparatus of my invention.

In the illustrated embodiment, the position of the characters on theprint wheels 1 is registered by an index pulse generator 3 and acharacter pulse generator 4, both controlled by the print wheel driveshaft 2. The index pulse generator 3 comprises a ferromagnetic disc 5mounted on the shaft 2 and provided with a single projecting tooth 6.The tooth 6 cooperates with a magnetic pickoff comprising aferromagnetic frame 7 mounted on a suitable support, not shown. Asschematically indicated, the frame comprises part of a magnetic pathwhich includes the body of the disc and two air gaps, one a constant gapbetween the end 7a of the frame 7 and the body of the disc 5, and avariable gap between the other end of the frame and the periphery of thedisc 5. Flux may be provided in this path by magnetically polarizing thetooth 6 with respect to the body of the disc 5, by magnetizing the frame7, or both. An index pulse is induced in a coil 8 wound on the frame 7as the tooth 6 passes the frame, thus momentarily reducing the secondair gap. The location of the tooth 6 on the periphery of the disc 5 withrespect to the characters on the print wheels 1 and the frame 7 is suchthat an index pulse is generated just before a predetermined firstcharacter in each font passes before the associated print hammer, sothat the index pulse indicates the beginning of a scan of the characterson the print wheels.

The character pulse generator 4 may be similar to the index pulsegenerator, except that it is arranged to emit a pulse just before eachcharacter arrives in printing position. As shown, it may comprise aferromagnetic disc 9 provided with a plurality of projecting teeth suchas 10, the disc being fixed on the shaft 2 for rotation therewith andadapted to cooperate with a relatively fixed magnetic frame 11 on whicha pickoff coil 12 is wound. As described for the index pulse generator,the teeth 10, the frame 11, or both, are magnetically polarized. Therelative arrangement of the parts is such that, just before eachcharacter arrives in printing position, a character pulse is induced inthe coil 12. The reason for anticipating the arrival of the charactersby a small amount is that time must be allowed for the electricalsystem, to be described, to function, and for the hammer to move theshort distance necessary to print the character as it arrives inposition.

By conventional apparatus, which it is unnecessary to describe indetail, the record sheet and transfer ribbon are stepped forward afterthe printing of each line, and during this period data for a new line issupplied. After the record sheet is in position and the new data hasbeen stored, a print cycle is initiated in which the stored data isdecoded and the corresponding characters are printed. Since theapparatus of my invention is involved only in the control of the printhammers during the print cycle, the apparatus for initiating this cyclehas been schematically shown as a manually operable switch 13, closedwhen it is desired to print a line of characters to supply a print pulseto the system from a suitable power supply, here schematically shown asa battery 14.

When the switch 13 is closed, a positive pulse from the battery 14 iscoupled through a suitable capacitor C1 to an input terminal b of aconventional bistable multivibrator, or flip-flop, FFl. This flip-flop,as well as other flip-flops to be described, may be of any suitableknown construction having complementary output terminals set to a firststate in response to a pulse applied to one of two complementary inputterminals and to an opposite state in response to a pulse applied to theother input terminal. A suitable circuit is shown, for example, in Fig.198 on page 203 of TMl169(l, Basic Theory and Application ofTransistors, published in March, 1959 by Headquarters, Department of theArmy. The output terminals and d of the flip-flop FF 1 may be connectedto the collectors of the transistors Q1 and Q2 in the publication. Thebias voltages will be assumed to be such that in one state of theflip-flop FFI, its output terminals 0 and d are at ground and a positivevoltage, respectively, and in the other state, at the positive potentialand ground, respectively.

The other input terminal a of the flipflop FFl is connected to an outputterminal f of a binary counter 26, to be described. The connections aresuch that when the switch 13 is closed, the pulse applied to the inputterminal b of the flip-flop FFl drives it to a logical 1 state in whichits output terminal 0 is positive. After completion of the printingoperation, the binary counter 26 applies an end-of-print" pulse to theinput terminal a of the flip-flop FFl, to reset it to a logical 0 statein which the terminal c is at ground potential.

When the flip-flop FFl is in its logical 1 state, a positive voltagelevel from its output terminal 0 is applied over the lead 15 to energizea data source schematically indicated at 17. The data source 17 may beany conventional storage unit, provided with gating means for enteringand extracting character data in any selected digital code. As hereschematically shown, however, it

may comprise a series of groups of switches, such as the groupcomprising the switches 18, 19, 20 and 21, which may be manually set ina binary code sequence corresponding to a selected character to beprinted, with the lowest ordered bit represented by the switch 18; thus,the sequence 1101 would be represented by 18 closed, 19 open, and 20 and21 closed. One such group of switches is provided for each character inthe line, and as many characters as are desired may be provided for; forsimplicity, however, I have shown apparatus for handling only twocharacters; the switches 22, 23, 24 and 25 provide storage for thesecond character.

During the print cycle, when the flip-flop FFl is in its logical Istate, data stored in the data source 17 is applied to comparators, onefor each character to be printed. Thus, the character code representedby the state of the switches 18, 19, 20 and 21 is applied to the inputterminals a, b, c and d, respectively, of a comparator CPI, and thecharacter code represented by the state of the switches 22, 23, 24 and25 is applied to the input terminals a, b, c and d of a comparator CP2.The internal construction of these comparators will be described indetail below.

The output terminal 0 of the flip-flop FFl is also connected over thelead 15 to one input terminal of a conventional AND gate A1. This ANDgate, as well as other AND gates to be described, may be of anyconventional construction, and, for example, may be of the type shown inFIG. 208A on page 213 of the above cited TMll-690. For convenience, itwill be assumed that a positive input voltage provides a positive outputpulse in this gate, so that an n-p-n transistor, with appropriate biaspotentials, would be employed instead of the p-n-p type shown in thepublication.

The output of the AND gate A1 is connected to one input terminal a of asecond flip-flop FFZ, which may be of the same construction as theflip-flop FFl. The output terminal a of the index pulse generator 3 isconnected to the other input terminal of the AND gate A1 and to theinput terminal b of the flip-flop FFZ. The output terminal 0 of theflip-flop FF2 is connected to one input terminal of an AND gate A2, andthe output terminal a of the character pulse generator 4 is connected tothe other input terminal of the AND gate A2. During the paper feed andcharacter loading portion of the printer cycle, when the flip-flop FFlis in its 0 state, the shaft 2 makes one or more complete revolutions,and the index pulse generator 3 emits at least one index pulse. Thispulse will set the flip-flop FFZ to a state in which its output terminal0 will be at a potential, representing a 0 logical level, which will notpermit the AND gate A2 to pass character pulses emitted by the characterpulse generator 4. Repeated index pulses will not atfect the state ofthe fiipfiop F1 2, 50 that the AND gate A2 will remain cut off until theprint cycle is initiated by the closing of the switch 13.

When the switch 13 is closed, the flip-flop FFl goes to its 1 state andthe AND gate A1 is enabled to pass the next index pulse to set theflip-flop F1 2 to its opposite state; the concurrent application of theindex pulse to the flip-flop on the opposite terminal will have noeffect, as is known in the art and will be apparent from a considerationof the circuit detailed in Fig. 198 of TMl l690, cited above. With theflip-flop FF2 in its opposite state, a logical 1 in the form of apositive voltage will be applied to the AND gate A2 to enable it to emita pulse for each applied character pulse until the next index pulse.Since the pulses emitted from the AND gate A2 are thus keyed to thepreceding index pulse, they identify the characters coming into printingposition on the print wheels in the sequence in which they appear, andone set of character pulses so emitted represents one completesequential scan of the character fonts. This sequence is used togenerate a character scanning code having a unique code sequence foreach character on the print wheels, in a manner which will be made clearbelow.

The output terminal of the AND gate A2 is connected to one inputterminal of each of the AND gates A3, A4, A5 and A6. The other inputterminal of each of these gates is connected to a dilTerent one of theoutput terminals b, c, d and e of a scan code generator, here shown as abinary counter 26. While any conventional code generator capable ofemitting a predetermined sequence of digital code sequences could beemployed for this purpose, one suitable binary counter is shown whichcomprises four trigger circuits T1, T2, T4 and T8, whose referencenumerals indicate the relative binary order of the output of eachtrigger circuit. These trigger circuits are interconnected to form abinary counter which will generate code sequences in descending binaryorder on its output terminals b, c, d and e in response to successivepositive-going input pulses applied to its input terminal a. The triggercircuits may be constructed in the manner shown in detail in Fig. 15.54on pages 1555 of Hunter, Handbook of Semiconductor Electronics,published in 1950 by the McGraw-Hill Book Company, Inc., although anyother suitable circuit could be employed, if so desired, withoutdeparting from the scope of my invention. The details of these circuitsand their mode of operation are explained in the reference publication;it is sulficient for the understanding of my invention to point out thatin response to a positive-going pulse applied to the central inputterminal b of a trigger circuit such as T1, its complementary outputterminals e and d will switch from one state to an opposite state, andthat a succeeding pulse will switch these terminals back to theirinitial state. The binary zero state is assumed to be the one in whichterminal e of the trigger circuit T1 is at ground potential and terminald is at a positive potential. In the binary 1 state, terminal e will beat a positive potential and terminal a will be at ground potential. Inpassing from the 1 state to the 0 state of the trigger circuit, apositive-going pulse will be transmitted through a capacitor C3 from theoutput terminal e of the trigger circuit T1 to the central inputterminal of the trigger circuit T2, causing it to reverse its state. Theoutput of the trigger circuit T2 is similarly connected to the input ofthe trigger circuit T4, and the trigger circuit T4 is connected to thetrigger circuit T8, in the manner shown in the drawing. apparent tothose skilled in the art that with these connections, a series of inputpulses will cause the trigger circuits to change state, TI on eachpulse, T2 on every other pulse, T4 on every fourth pulse, and T8 onevery eighth pulse. Thus, the output terminals 0 of the trigger circuitswill cycle through the binary sequence 0000. 0001, 0010, 0011, etc.,while the output terminals d will cycle through the complementarysequence 1111, 1110, 1101, 1100, etc. At the seventeenth pulse, thecounter will be reset to zero and the count will begin anew. As shown inFIG. 1b, the complementary output terminals 0! of the trigger circuitsare connected to the output terminals 12, c, d and e of the counter. Thereason for the selection of the complementary sequence for the characterscan sequence will be made apparent below.

The output terminal e of the trigger circuit T8 is connected through asuitable coupling capacitor C6 to an output terminal f of the counter.At each seventeenth input pulse, a positive-going pulse will be appliedto the terminal f, which pulse is used as an end-of-print" signal in amanner set forth in detail below.

It is desired to produce this end-of-print pulse after the end of eachcharacter scan. Accordingly, a connection is made through suitableisolating diodes, as shown, to the input terminal c of each of thetrigger circuits to apply a pulse through the capacitor C1 at thebeginning of each print cycle, to set all of the trigger circuits totheir logical zero states. Thus, the counter will always start at zeroand the first input pulse applied to input terminal a of the counterwill step the counter to its second state, so that It will be i theoutput pulse will appear at terminal on the sixteenth input pulse. Afterthe first cycle of operation, the pulse applied to terminals c of thetriggers will have no elfect, because the counter will be in the zerostate when their pulse is applied.

While the counter and the data source have been described in terms of afour-bit code, it will be apparent that characters requiring larger orsmaller codes could be employed without requiring more than an obviousextension or contraction of the system.

It will be seen from the above description that at each character pulsegated to the AND gates A3, A4, A5 and A6 by the AND gate A2, the codestored in the counter 26 will be gated to the input terminals f, g, hand i of the comparators CPI and CP2. As each code sequence in the scanis thus applied to the comparators, it is compared with the charactercode stored in the comparator. At the same time, a sample pulse isapplied to the input terminal i of each comparator, and, if thecharacter then coming into position on the print wheels, whichcorresponds to the scan code sequence, is a member of the setcomplementing each 1 in the character code for the stored character in agiven comparator, the sample pulse is gated to the output terminal 6 ofthe comparator. The output terminal e of each comparator is connected toan input terminal a of a print hammer driver circuit, such as DRI andDR2, to be described. The print hammer drivers are controlled by ahammer drive control unit 27, to be described, which controls the printhammer drivers in such a way that, at the first pulse applied to theinput terminal a of a print hammer driver such as DRI during a givenprint cycle, the associated print hammer coil such as HC1 is energizedto print the character then in position. However, succeeding pulsesduring the same print cycle will not cause energization of the printhammer coil. The necessity for this mode of operation will be madeapparent below.

The output of the AND gate A2 is also applied to the input of a suitabledelay line D1. This unit, as well as other delay lines to be described,may be of any conventional construction for example, it may be of thetype shown and described in my United States application Serial No.106,840, filed May l, 1961, for Pulse Retiming System, which is assignedto the assignee of this application. It is sufficient for theunderstanding of my invention to note that the delay line D1 willproduce a positive-going output pulse a predetermined time after apositive-going input pulse is applied.

The output pulses produced by the delay line D1 are applied to the inputterminal a of the counter 26, so that the counter is set to the nextbinary state after its current state has been gated to the comparators.The reasons for this mode of operation are, first, that it is necessaryto use the zero state of the counter in the character scan sequence, aswill appear, and second, that it would be undesirable to gate thecounter output during a change of its state.

Refer now to FIG, 2, in which the details of the comparators, the printhammer driver, and the hammer drive control unit 27 are shown.Considering first the comparators, all of these units may be identical;therefore, only the unit CPl is shown in detail. As shown, each bit ofthe stored character code (from the data source 17 in FIG. lb) isapplied to one input terminal of a different one of four AND gates A7,A8, A9 and A10. The corresponding bit of the character scan code (fromthe counter 26 in FIG. 1) is applied to the other termi nal of theassociated AND gate. Thus, each of the AND gates A7, A8, A9 and A10 willproduce a positive output potential, corresponding to a logical 1 level,if and only if both of the input bits are positive, corresponding tological 1 levels.

The outputs of the AND gates A7A10 are applied to a logic unit LUI,which is typical of the other similarly designated units to bedescribed. In this unit, the output terminals of the AND gates A7, A8,A9 and A10 are connected to the input terminals of an OR gate ORl. ThisOR gate may be of any suitable construction capable of producing apositive output pontetial in response to a positive potential applied toany one or more of its four input terminals, such as the OR gate shownin Fig. 206A on page 211 of the above-cited TMll-690, which may beprovided with additional input terminals as pointed out on page 211.

The output of OR gate R3 is connected to the 3* input terminal of an x17gate 28. A suitable circuit for the gate 28 is shown in Fig. l5.43(a) onpages l5-46 of the above-cited Handbook of Semiconductor Electronics. Itwill suffice for the understanding of my invention to note that thiscircuit will produce a positive potential on output terminal 1 of thelogic unit LUl if and only if a positive potential is applied to itsinput terminal x but not to its input terminal y. As shown, the samplepulses (from the AND gate A2 in FIG. 1) are applied to the terminal ofunit 28, so that a print command pulse will appear at output terminal eof the comparator CPI if and only if a sample pulse has been applied tothe input terminal j of the comparator, and no two corresponding bits ofthe stored character and character scan codes are both logical ls.

Assume for simplicity that there are 16 characters on each print wheel,and identify their order of appearance in printing position following anindex pulse by the numerals from 1 to 16. Let the stored characters becoded from 0 to in the ascending binary sequence. For each character,the corresponding codes will then be given by the following table:

To illustrate the mode of comparison, suppose that character number 12was stored for the print Wheel cor- 8 the inputs and outputs given bythe following table, in which C represents a stored character code inputbit, S represents a scan code input bit, and 0 represents the output ofthe AND gate, with positive potentials being indicated by logical 1, andground potential or an open terminal indicated by logical 0:

Gate

Character number A10 A9 A8 A7 0 S O G S O (l S O C S 0 1 1 t] 1 U 1 1 11 1 1 1 1 t] 1 0 1 1 1 1 t) 0 1 1 0 1 l) 1 0 (l 1 1 1 1 1 0 1 0 1 0 l] 1t) t) 1 1 0 0 D 1 1 1 1 1 1 1 1 t] t) l) 1 1 1 1 0 i I) 1 1 0 0 0 1 U 01 1 1 0 1 0 t) 0 1 0 0 1 0 D O 0 U 1 t) 1 t 1 1 1 1 1 l) (I l] 1 l) 1 11 l U 0 0 0 U 1 0 1 (I 0 1 1 1 0 0 0 l t) 1 ti 0 1 (l i 0 0 0 0 t1 0 1 11 1 1 1 0 0 (1 t1 t1 1 1 1 1 0 0 1) O O 1) 0 1 0 0 1 1 1 U 0 O 0 I) 1 U0 1 0 0 It will be seen that none of the AND gates A7, A8, A9 and A10will produce an output in response to the scan codes corresponding tocharacters 12 and 16, and that at least one of the AND gates willproduce an output in response to every other scan code. Referring toFIG. 2, it will be recalled that logic unit LUl will emit a printcommand pulse when and only when a sample pulse is applied to its inputterminal x and none of the AND gates A7, A8, A9 and A10 supply a pulse,through the OR gate 0R1, to the input terminal y of the unit LUl.Accordingly, a print command pulse will be pro duced only when the 12thand 16th characters come into position. As will appear, the print hammerdrivers such as DRI will energize their hammer drive coils such as HClonly once during a print cycle, so that only the 12th character on theprint wheel will be printed in the example here considered.

The operation of the comparator with other stored character codes may beseen from the following table, in which the scan codes which will causea print command pulse to be generated for each stored character codewhich may be supplied to a comparator are indicated by an x in thecolumn designated by the decimal value of the binary numbercorresponding to the stored character.

Character Number Character Scan Code Stored Character Code (DecimalValue) wwauaaawaaaaa l c responding to comparator CPI. The inputterminals a, b and d of the comparator CPI and then be at a positivepotential, and the input terminal c would be open, representing thecharacter code 1011. As the scan progressed following the first indexpulse in a given print cycle, the AND gates A7, A8, A9 and A10 wouldhave Since it is readily implemented with a simple binary counter, thedescending binary code sequence is preferred for scanning in thecomparator of my invention. However, a large number of other scan codesequences is possible, which sequences may be obtained by reordering thedescending binary sequence in such a way that each scan code sequenceapplied to the comparators will produce an output with one and only onecharacter code in addition to those previously scanned. A typicalrearrangement is shown in the following table, using a three bit codefor concisencss; eight characters on the print wheels are assumed.

Character It will be seen that a stored character represented by binaryzero (000) will respond to any scan code, and any scan code other than111 will also produc a response with at least one other character code.Thus, a principle of reordering is that if 000 is not excluded, 111 mustbe the first scan code. Also, any character code will respond to thescan code 000, so that if this scan code is used, it must be last in thescan sequence. If desired, the scan code may be truncated, as wherefewer characters than a full binary set are used, by taking away thelast sequences in the scan code first.

More specifically, a scan code sequence in which there are m Os willproduce a response with 2 1 character code sequences, including the zerosequence 000 0. Thus, if such a sequence is designated as Sm, and therespouse is to be unambiguous, Sm must be preceded by a set of 2 --2other scan code sequences besides the sequence 11 1 and not includingthe zero sequence, which include fewer than m 0s and which would producea response with all but one of the sequences with which Sm would producea response. For example, if the sequences are ranked in sets inaccordance with the number of 0s as S S S S,,, then they might bearranged in that order with the individual members of the sets S 5,,etc., arranged in random order to form a class of scan code sequencesoperative in the comparator of my invention. However as illustrated bythe descending binary sequence, it is not necessary to exhaust all ofthe sequences containing less than m 0s before introducing a sequenceSm, but only to scan for all of its possible l-complementing sequencesexcept the full complement, which contains in 1s. Thus, the first scancode sequence containing two Os must be preceded by 2 2:2 scan codesequences each containing one 0. For example, the sequence 1011011 mustbe preceded by the sequences 1011111 and 1111011, in either order, toexclude all of the character codes except 0100100. However, the next Ssequence may be added following only one additional 5, sequence, if itis related to one of the previous S, sequences. Thus, 1111101 could beadded to the sequence, followed by 1011101. A scan code beginning asfollows might then be formed:

Stored Character (lode In which the responses are indicated by the X'sand the character codes causing the responses are represented by theirdecimal equivalents, as before. In this example, the character codes arescanned in the order 0, 32, 4, 36,

In general, sequences other than the normal descending binary willrequire a pattern generator other than the simple binary counter, Onesuitable pattern generator for generating any desired code sequence maybe made by mounting a series of toothed discs, such as the characterpulse generator disc 9 in FIG. 1, on the shaft 2, each provided with apickofi? coil such as 12 in FIG. 1, and each having selected teethremoved to produce a sequence of logical 1 and 0 levels as each toothposition passes the pickoff coil.

Referring again to FIG. 2, the hammer drive control unit 27 and theprint hammer driver DRl will next be described. Since the other printhammer drivers, such as DRZ, are the same as DRl, and are controlled inthe same way by the hammer drive control unit 27, they will not bedescribed in detail.

The hammer drive control unit 27 comprises a silicon controlledrectifier S1, having its load terminals a and b connected in series withthe secondary winding 29 of a pulse transformer PT1, a suitable currentlimiting resistor R1, and a suitable source of voltage such as a batteryB1. A conventional diode 30 is connected between the base terminals band c of the controlled rectifier S1 as shown. A suitable couplingcapacitor C9 is connected between an input terminal a of the controlunit and the base terminal 0 of the controlled rectifier S1, whichserves to couple an applied positive-going end-ofprint pulse to the baseterminal 0. The pulse transformer PT1 is provided with a primary winding31, connected between input terminal I: of the unit 27 and ground; whenthe switch 13 in FIG. 1 is first closed, this winding 31 induces ablocking pulse in the winding 29, for purposes to be described.

As is well known in the art, a controlled rectifier such as S1 will notconduct current in response to a forward biased voltage across its loadterminals unless its control base terminal such as c is biasedpositively with respect to its load base terminal such as b. Thereafter,the controlled rectifier will continue to conduct, regardless of thebias potential, until the current in the load circuit is interrupted.Assuming that the controlled rectifier S1 is not conducting, a positivepulse applied between the input terminal a of the unit 27 and groundwill switch it to its conducting state, causing load current to flowthrough the secondary winding 29 of the pulse transformer PT1 and theresistor R1. This current will continue to flow until a start printpulse is applied to the secondary winding 29 of the pulse transformerPT1 by the primary winding 31 in response to the closing of the switch13 in FIG. 1b. This pulse will momentarily reverse-bias the controlledrectifier, causing it to switch back to its non-conducting state. Thus,during the interval between an end of print pulse applied to the inputterminal a of unit 27 and an ensuing start print pulse applied to theinput terminal I), a voltage will appear across the output terminals 0and d of the unit 27, which voltage is used as a supply for the printhammer drivers.

A print hammer driver such as DRl is provided for each hammer drive coilsuch as HCl. As shown, the hammer drive coil HCl is connected in serieswith the load circuit of a silicon controlled rectifier S2, of the sametype as the silicon controlled rectifier S1 in the hammer drive controlunit 27. The hammer coil HCl is at times energized, under conditions tobe set forth, through a circuit extending from the positive terminal ofan electrolytic capacitor C7 through a variable current trimmingresistor R2, the hammer coil HCl, the controlled rectifier S2 in itsconducting state, and back to the negative terminal of the capacitor C7.A conventional diode 33 may be connected across the capacitor C7 asshown, to protect it against transient negative voltages.

A charging circuit for the capacitor C7 extends from the output terminal0 of the hammer drive control unit 27 through a conventional diode 32,which serves to isolate the print hammer driver DRl from the other printhammer drivers, a current limiting resistor R3 which serves to time thecharging of the capacitor C7, the current trimming resistor R2, thecapacitor C7, and thence to the grounded terminal d of the hammer drivecontrol unit 27.

A control circuit for the controlled rectifier S2 is provided in thesame manner as for the controlled rectifier S1. Thus, a blocking diode34 is connected across the base terminals b and c of the controlledrectifier S2, to prevent the control base terminal c from going negativeduring conduction between the input terminal a and the base terminal b,and also to permit the control terminal c to be biased positively withrespect to the base terminal b when it is desired to switch thecontrolled rectifier S2 to its conducting state. A capacitor C8 isconnected between the base terminal of the controlled rectifier and theoutput terminal e of the comparator CPI, to couple a positive pulse tothe base terminal c for each print command pulse emitted by thecomparator.

It is desirable to discharge the capacitor C7 much more rapidly than itis practical to charge it. Accordingly, in the hammer driver circuit,the resistance of the current trimming resistor R2 is preferably muchless than that of the current limiting resistor R3, so that thedischarge time of the capacitor C7 may be quite short with respect tothe charging time.

The operation of the print hammer driver DR1 may best be consideredbeginning with the conditions prevailing just before the start of theprint cycle. At this time, the controlled rectifier S1 in the hammerdrive control unit 27 is conducting, and charging current is supplied tocharge the capacitor C7, through the charging circuit previously traced.

When a print cycle is initiated by closing the switch 13 in FIG. 1b, astart print signal is supplied to the hammer drive control unit 27 inthe manner described above, and the output terminal c of the hammerdrive control unit will go to ground potential. Discharge of thecapacitor C7 is blocked at this time by the diode 32 and the controlledrectifier S2 in its non-conducting state.

At some time during the rotation of the print wheel shaft 2 in FIG. 1a,the character code stored at the input terminals a, b, c and a of thecomparator CPI in FIG. 2 will match the scan code applied to its inputterminals f, g, h and i, and a print command pulse will be applied tothe input terminal a of the print hammer driver DR1 in the mannerdescribed above. This print command pulse will switch the controlledrectifier S2 to its conducting state, and the capacitor C7 will bedischarged through the hammer drive coil HCl, causing the storedcharacter to be printed. With the capacitor C7 discharged, anysucceeding print command pulses emitted by the comparator CPI will beineffective.

At the end of the scan sequence, the counter 26 in FIG. 1b will emit anend-of-print pulse, which will reset the controlled rectifier S1 in thehammer drive control unit 27 to its conducting state. Thereafter,charging current will be supplied to the capacitor, such as capacitorC7, of the print hammer driver circuits, until the next print cycle isinitiated.

The overall operation of the embodiment of my invention just describedwill next be described with reference to FIGS. la, 1b, and 2. Since theoperation of the apparatus for each column to be printed is the same,only the printing of a single character in the first column, using theprint wheel P1, will be described. Using the binary scan and charactercodes given above, assume that it is desired to print the fourthcharacter on the wheel P1, for which the corresponding code is 0011.This code is first stored in the data source 17 by closing the switches18 and 19. It is assumed that the motor M is in operation, and that theprint wheels 1 are rotating. Next, the switch 13 in FIG. lb is closed,causing the flip-flop FFl to produce a positive voltage level on itsoutput terminal 0. This voltage performs three functions. First,referring to FIG. 2, it produces a pulse output across the sec ondarywinding 29 of the pulse transformer PTl, which cuts off the controlledrectifier S1, and restores the output terminal 6 of the hammer drivercontrol unit 27 to ground potential. This action terminates the chargingof the print hammer driver DR1 as previously described. Second, theapplication of a positive voltage to the lead 15 applies the data storedon switches 18, 19, 20 and 21 to the input terminals 0, b, c and d ofthe comparator CPI, so that the terminals c and d are open and terminalsa and b are at a positive potential. Third, the AND gate A1 is enabledto pass the next index pulse.

When the tooth C on the index pulse generator disc 5 passes the frame 7,a pulse is applied to input terminal a of the flipflop FF2, which has noeffect because the flip-flop is already in its logical 0 state, and thepulse is also applied through the AND gate A1 to the input terminal b ofthe flip-flop FFZ, causing it to shift to its logical 1 state. Thisaction enables the AND gate A2 to pass the next character pulse.

As the character pulses are generated, the AND gate A2 performs threefunctions. First, a sample pulse is applied to the input terminal 1' ofthe comparator CPI. Second, during each character pulse the AND gatesA3, A4, A5 and A6 are enabled to apply the potentials appearing on theoutput terminals 17, c, d and e of the binary counter 26 to the inputterminals 1', h, g and 1, respectively, of the comparator CPI. Third,each character pulse is applied to the delay line D1. A delayed timethereafter, the delay line D1 then applies a pulse to the input terminala of the binary counter 26 to shift it to the next state. Referring nowto FIG. 2, in the example given, the terminals 0 and d of the comparatorCP1 are unenergized, and the input terminals a and b are energized.Thus, the AND gates A9 and A10 are cut off and the AND gates A7 and A8are enabled to produce a pulse for any logical one in the scan codeapplied to terminals f and g. As the fourth character comes intoposition, the scan code 1100 will be generated, and terminals l1 and iof the comparator CPI will both be at ground potential. Accordingly,there will be no input to the OR gates in the logical unit LUl, so thatthe sample pulse simultaneously applied to the A. terminal of the .117circuit will cause a print command pulse to be applied to the inputterminal a of the print hammer driver DR1. The capacitor C7 will thendischarge through the hammer drive coil HC1 in the manner previouslydescribed causing the fourth character on the print wheel P1 to beprinted. Print command pulses will also be emitted on the eighth,twelfth, and sixteenth. scan code sequences, but, with the capacitor C7discharged, these signals will be ineffective.

After the sixteenth character pulse, the binary counter 26 emits anend-of-print pulse, which performs two functions. First, it is appliedto the input terminal a of the hammer drive control unit 27 in FIG. 2 torestore the controlled rectifier S1 to its conducting state and resumethe charging of the capacitors in the print hammer drivers. Second, itis applied to the input terminal a of the Hipflop FFl to restore it toits 0 state, thus disabling the data source 17 and the AND gate A1 inFIG. la.

The next index pulse emitted by the generator 3 will restore theflip-flop F1 2 to its 0 state, disabling the AND gate A2. Since theflip-flop FF1 cannot be reset until the switch is again opened and thenclosed, additional index pulses and character pulses which may occurwill be ignored. When the switch 13 is opened, the apparatus will berestored to its original condition.

Referring now to FIGS. 3a and 3b, a modification of the apparatus of myinvention for use with transient data presented serially in parallelform is shown. Data may be supplied to the system by applying charactercodes, one code sequence at a time, to the input terminals (1, b, c andd in FIG. 30. Thus, for example, assume that the fifth character on theprint wheel PI, having the character code 0100!, was to be stored, apositive pulse would momentarily be applied to input terminal b in FIG.30. It is assumed that together with each character code an additionalpulse will be applied to an auxiliary input terminal m, which will betermed a load character pulse. Suitable apparatus for supplying data inthis form is well known, and need not be described. If desired, it couldbe supplied by a manually set switches in the manner shown in FIG. lb.

Before describing the details of the system of FIGS. 3a and 3b, thearrangement of the components and their functions will be brieflydescribed. In general, the apparatus is adapted to be used with aprinter of the type described in connection with FIGS. la and 11),provided with a series of print wheels, each having a hammer controlledby one of the print hammer drivers DRI, DR2, DRn, which may be identicalwith the print hammer drivers DRI shown in FIG. 2. These print hammerdrivers are controlled by a hammer drive control unit 7, shown in FIG.3b, which is shown in more detail in FIG. 2. The index pulse generator 3and character pulse generator 4 are the same as those units shown in thepreviously described emobdiment, as is the counter 26.

The print command signal for each print hammer driver is provided by anassociated logic unit, such as LUI, LUZ and LUn. These logic units maybe of the construction shown for unit LUI in FIG. 2. In the system shownin FIG. 3a, the data for each character to be printed is shifted througha series of storages until it is stored in a storage unit associatedwith the proper print hammer driver. Thus, for the first print hammerdriver DRI there is provided the first storage unit SIA for the firstbit of the character code, and storage units SIB, SIC and SID for theremaining bits of the character code. Associated with the print hammerdriver DRZ is a similar series of storage units, SZA, SZB, SZC and 52D.Likewise, the nth print hammer driver DRn, as well as intermediateunits, is provided with a series of storages SnA, SnB, SnC and SnD. Asit will appear, considering only the first bit of the character code,which corresponds to the nth column to be printed, it is first stored inthe unit SIA, then shifted into the storage unit 82A, and finally intothe storage SnA, from which it is transferred to the logical unit LUn,together with the remaining bits of the character code stored in theunits SnB, SnC and SnD, to actuate the print hammer driver DRn when theappropriate scan code is generated. The manner in which this function iscarried out will be made clear below.

The input terminals a, by, c and (I in FIG. 3a are con nected to theinput terminals a of a series of flip-flops FF3, FF4, FFS and FF6. Theapplication of a positive pulse to these input terminals of theflip-flops will cause them to shift to their logical 1 states in whichtheir output terminals a are at ground potential. These terminals areeach connected to one terminal of an output coupling capacitor, such asthe capacitor 45 shown for the flip-flop FPS, and the other terminal ofeach capacitor is connected to ground through a suitable clamping diodesuch as the diode 46. Thus, setting of the flip-flops to their logical 1states will not produce an output pulse, because the diode 46 will notpermit the output to go below ground, but resetting them to theirlogical states will produce positive-going output pulses.

The terminal m to which the load character pulse is applied is connectedto the input terminal of a delay line D2, which may be of the same typeas the delay line D1 in FIG. 1a. The output of the delay line D2 isconnected to the input terminals b of the flip-flops FF3, FF4, FFS andFF6. Thus, each flip-flop is reset a delayed time after each charactercode is presented to it, causing it to emit a positive pulse if alogical one, or a positive pulse, was presented to the input terminal aof that flipflop by the applied character code.

The input terminal in is also connected to one input terminal of each ofa group of OR gates 0R4, 0R5, 0R6 and 0R7, which may be the same as ORgate 0R1 in FIG. 2, except that they include only two input terminals.The output of these OR gates are connected to a series of driveramplifiers 40, 41, 42 and 43. The functions of these amplifiers will bedescribed after describing the storage units in somewhat more detail.

Referring now to the storage unit SIA, this unit comprises a switch coreSCI of saturablc ferromagnetic material, which is provided with fourwindings a, b, c and d. An energizing circuit for the winding (1 of theswitch corc SCI extends from the output of the flip-flop FF3 through thewinding a, through an isolating diode 47, and over a common lead 48 tothe output terminal 0 of the flip-flop FF2, for purposes to bedescribed. Thus, a positive pulse from the flip-flop FF3 will causecurrent to flow through the winding (1 of the switch core SCI, drivingit to saturation in one direction, if the flip-flop FF2 is in itslogical 0 state. with its output terminal c at ground potential, but ifthe flip-flop FF2 is in its logical 1 state, the diode 47 will beblocked and will prevent the flow of current through the winding a. Thewinding c of the switch core SCI is connected to a delay unit DZA,comprising a conventional diode 49 and a capacitor 50. The output of thedelay unit DIA is connected to one terminal of the input winding (1 of aswitch core SCZ in the second storage unit 52A. The other terminal ofthe winding a on the core SC2 is connected through a blocking diodc 51to the common lead 48, which is in turn connected to the output terminalc of the flip-flop FF2.

The output of the delay unit DIA is also connected to one terminal ofthe winding b of the switch core SCI. The other terminal of the windingb is connected through a blocking diode 52 to a common lead 53. Asshown, the common lead 53 is connected to the output terminal d of theflip-flop FF2.

With these connections, it will be apparent that a voltage induced inthe winding c will not cause an output pulse from the delay unit DIAunless it is positive-going, and that a positive-going pulse which doesproduce an output will be effective to cause current to flow through thewinding (1 of the switch core SCZ if the flip-flop FF2 is in its logical0 state, but not with it in its logical 1 state, and will cause acurrent to flow through the winding b of the core SCI in the logical Istate of the flip-flop FF2 but not in the logical 0 state. The utilityof these connections will he made to appear.

The windings d of each of the switch cores SCI, SC2 and 8C3 areconnected in series to the output terminals of the amplifier 40 in FIG.3b. Similar connections are made to the output terminals of amplifiers41, 42 and 43, from the switch cores in the remaining storage units.When the associated OR gate produces a positive pulse, each amplifierproduces a negative pulse, which serves to shift each switch core to thesaturated state opposite to that which a positive pulse applied to itswinding a would produce.

Referring now to FIG. 3b, the print cycle may be initiated inessentially the same way as described in connection with FIGS. 10 and1b. Thus, the closing of the switch 13 applies a pulse from the battery14 through the capacitor C1 to set the flip-flop FFI to apply a positivevoltage to the lead 15. The control of the AND gates A1 and A2 and theflip-flop FF2 may be the same as that described for the firstembodiment. Also, the AND gates A3, A4, A5 and A6, may be connected inthe same way to the output of the counter 26. As before, the delay unitD1 applies pulses to the counter 26 a delayed time after the AND gatesA3A6 sample the scan code stored in the counter, and at the end of thescan an end-of-print signal is applied by the counter 26 to reset theflip-flop FFI. In this embodiment, the delay of the delay line D1 ismatched to the delays of the units such as DIA, D2A, etc., in thestorage units, for reasons which will appear.

The hammer drive control unit 27 is sequentially operated by the startprint signal from the flip-flop FFI and the end-of-print signal from thecounter 26, to control the charging of the capacitors in the printhammer drivers DRI, DRZ, etc., in the manner described above inconnection with FIGS. la and lb and 2, and this description will not berepeated.

The operation of this embodiment of my invention will now be described,assuming that the 9th, lst, and 13th characters are to be printed in thefirst, second and last columns of a line to be printed. The characterfor the last column must be entered first, so that the characters willbe presented in the order 13, 1, and 9. Assume that the switch I3 isopen, so that the flip-flops FF] and FFZ will be in their logical 0states. Likewise, flip-flops FF3, FF4, FPS and FF6 may be assumed to bein their logical 0 states.

Loading of the first character, assumed to be the 13th H character inthe print wheel series having a character code 1100, is accomplished byapplying a positive pulse to the input terminals (1, b and m in FIG. 3a.Flip-flops F1 3 and FF4 will thus be set to their logical 1 states, inwhich their output terminals (1 are at ground potential. The pulseapplied to input terminal in actuates the OR gates 0R4. 0R5, 0R6 and 0R7to produce output pulses. These pulses are inverted by amplifiers 40,41, 42, and 43 respectively. This action produces a set of negativeoutput pulses; confining attention to the amplifier 40, its output pulseis applied to each of the windings d of the switch cores SCI, SC2 and802. In the initial state, each of these cores will be saturated, in amanner which will appear, in the same sense directed by the appliedpulse,

such that no output pulses will be produced. Accordi ingly, this pulse,and the similar pulses produced by amplifiers 4], 42, and 43, will haveno effect on the system.

Referring to FIG. 3a, a delayed time alter application of the loadcharacter pulse to input terminal m, the delay line D2 will produce anoutput to reset the flip-flop F1 3 and FF4 to their logical 0 states.Since the flip-flops FPS and FF6 are already in their logical 0 states,they will not be allectcd. However, the fiipfiops FF3 and F1 4 willproduce positive-going output pulses. The pulse from the llipdlop FPSwill cause current to flow through the winding :1 of the switch coreSCI, since the flip-flop FFZ is in its logical 0 state. The switch coreSCI will then be driven to saturation, causing a pulse to be inducedacross the windings b and c. However, the polarity of this pulse is suchthat it will be blocked by the diode 49, so that the delay unit DIA willproduce no output. The pulse produced across the winding [2 will be ofthe Wrong polarity to allect the logic unit LUI; in any event, no samplepulses are applied to the input terminals 0 of the logic units duringthe loading of characters. In a similar manner the pulse from theflip-flop F1 4 will be stored in the unit SIB.

Next, the first character, having the character code 0000, is stored byapplying a pulse only to the input terminal in. This pulse will be gatedthrough the OR gates 0R4, 0R5, 0R6 and 0R7 to cause amplifiers 40, 41,42, and 43 to produce outputs in the manner described above. Confiningattention to amplifier 40, since there is no storage in the switch coresSC2 through 801, the current through the windings d on the switch coresin these units will be ineffective. However, the current through thewinding 0. of the switch core SCI will drive the core to saturation inthe opposite sense to that produced by the previous pulse through thewinding a. This action will cause a pulse to be induced across thewinding 0 of the proper polarity to appear, a delayed time later, acrossthe capacitor 50. Since the diode 52 is blocked at this time, thisdelayed pulse will not cause current to flow through the winding b ofthe switch core SCI. However, it will cause current to flow through thewinding a of the switch core SCZ, causing it to be driven to saturationand storing a logical one in the same manner as the switch core SIA waspreviously set. The remaining storage units operate in essentially thesame way, such that the information previously stored in the storageunits SIA, SIB, SIC and SID is transferred to the stor' age units 52A,SZB, 82C and SZD.

The delayed pulse appearing across the capacitor 50 will be applied toinput terminal a of the logic unit LUI. However, since no sample pulsesare applied to input terminal e of the logic units during the loadingcycle, the presence or absence of pulses at input terminal a during thistime has no effect on the operation of the system.

A delayed time later, the delay line D2 will apply a pulse to theflip-llops FF3, FF4, FPS and FFG. Since all of these flip-flops arealready in their logical 0 states, no outputs will be produced. The nextoperations would be the loading of the characters between the lastcolumn and the second column. Since it is believed that this operationwill be apparent from the description given, it will be assumed thatonly three columns are provided, such that the Sn storages become the S3storages.

Next, the character for the first column to be printed, here assumed tobe the ninth character having the character code 1000, is entered byapplying a positive pulse to input terminals a and m in FIG. 3a. Theflip-flop F1 3 will be set to its logical I state. At the same time, thepulse applied to input terminal in will be gated to the amplifiers 40-43to energize the windings d of the switch cores. Assuming that there areno storages intervening between 82A and 511A, this pulse will cause thelogical l stored in switch core 5C2 to be transferred to the switch coreSC after the delay provided by the delay unit DZA. Since there is alogical stored in the switch core SCI, switch core SCZ will not bereset, but will remain in its logical 0 state. Next, the delay unit D2will produce an output, causing the flip-flop P1 3 to revert to itslogical 0 state which will store logical l in the switch core SCI. Theremaining bits of the character code are entered in their respectivestorages in the same manner as described for the first bits of each codegroup. Thus, at this time the character code for the ninth character isstored as a logical 1 in unit SIA and logical Us in units SIB, SIC andSID. The first character, having the character code 0000, is stored bylogical ()s in each of the storage units 52A, 52B, 82C and 52D. The 13thcharacter, having the character code 1100, is stored by logical 1s inthe unit 511A, and SnB, and by logical 0s in the unit 312C and SnD.

Next, the print cycle is begun by closing the switch 13. The flip-flopFFI will now be set to its logical 1 state to enable the AND gate AI, sothat the next index pulse from the generator 3 will produce an outputfrom the AND gate A1 to set the flip-flop FFZ to its logical 1 state.

With the flip-flop FF2 in its logical 1 state, its output terminal c isat a positive potential, enabling the AND gate A2 and blocking all ofthe a windings of the switch cores by cutting off their associatedblocking diodes, such as the diode 47 associated with winding (1 of theswitch core SCI. Terminal d of the fiip-fiop FFI is at ground potential,such that current may liow through the windings b of the switch cores.

At the first character pulse from the generator 4, the AND gate A2 willtransmit a pulse to the delay line DI and to the AND gates A3, A4, A5and A6. The output of the counter 26, which is 1111 at this time, isthen applied through AND gates A3-A6 and OR gates 0R4- 0R7 to amplifiers4043, respectively. Current is then supplied from the amplifiers 40-43to all of the windings d of the switch cores. Each switch core in thelogical I state will then be switched from saturation in one sense tosaturation in the opposite sense. In the example given,

the switch cores in the storage units SlA, SnA and SnB will be thusalfected. Considering the switch core SC1 in storage unit SIA, an outputpulse will be induced across the winding c which will appear, a delayedtime later, across the capacitor 50. Current will then flow through thewinding b of the switch core SCI, since the diode 52 is not blocked atthis time, and this current will again switch the core SCl to itslogical 1 state. In this manner, each time a logical 1 in a switch coreis erased by an applied scan code, it is rewritten in the storage by theoutput of the associated delay unit. The output of the delay unit DlAwill also be applied to the winding a of the switch core SC2 in thestorage unit SZA, but with the diode 51 blocked, no current will flowthrough the winding a and the switch core SC2 will remain in its logical0 state.

The output pulse from the delay unit DlA will be applied to inputterminal a of the logic unit LUl, and similar pulses will he applied toinput terminals a and b of the logic unit LUn from the delay units inthe storage units SnA and SnB. No pulses will be applied to the inputterminals a, b, c and d of the logic unit LU2, since none of the switchcores in the storage units SZA-SZD changes state.

At the same time, the pulse which was applied to the delay line D1 bythe AND gate AZ will appear at the output of the delay line. This pulseis applied to the input terminals e of the logic units I.U1, LUZ andLUn, and to input terminal a of the counter 26.

It will be recalled from the description of the logic unit LUl in FIG. 2that a print command pulse at terminal f will be produced if and only ifan input pulse is applied to terminal e and no input pulse is applied toterminals a, b, c and d. Thus, the logic units LUl and LUn will notproduce print command pulses, and logic i unit LUZ will apply a printcommand pulse to terminal a of the print hammer driver DRZ to print thefirst character in the second column.

The pulse applied to input terminal a of the counter 26 will shift thecounter to its next state, in which the output on terminals b, c, a' and2 will be 1110. At the next character pulse, this output will be gatedto the amplifiers 40-43, causing the amplifiers 40, 41 and 42 to produceoutput pulses. The operation of the storage units will be the same asfor the first scan code, in the example given, and only the logic unitLUZ will produce an output. However, this output will have no effectbecause the print hammer driver DRZ can operate only once during a printcycle.

The scanning will continue, in a manner which will be apparent from theabove description, until the ninth scan code, 0111, is gated from thecounter 26 to the amplifiers 40, 41, 42 and 43. Only the amplifiers 41,42 and 43 will produce output pulses. Thus, the switch core S01 will notchange state, and none of the switch cores in the units SIB, 51C and 51Dwill change state because they are already in the logical 0 state.Therefore, when the delayed character pulse is applied to input terminale of the logic unit LUl, a print command pulse will be applied to theprint hammer driver DR1 to print the ninth character in the firstcolumn.

As before, the logic unit LUZ will produce an output pulse, which willbe ineffective because the print hammer driver DRZ is discharged. Thelogic unit LUn will not produce an output, because a pulse will beapplied to its input terminal a by the storage unit SnA, and to itsinput terminal b by the storage unit SnB.

At the thirteenth scan code, 0011, output pulses will be provided by theamplifiers 42 and 43, which will be ineffective because no logical lsare stored in the storage units supplied by these amplifiers. No outputswill be provided by the amplifiers 40 and 41, so that no inputs will beapplied to the terminals a, b, c and d of the logic units LU1, LU2, andLUn. Thus, the delayed sample pulse from the delay line D1 will causeprint command pulses to be emitted from all of the logic units. Theprint hammer drivers DR1 and DRZ are already discharged, but the printhammer driver DRn will operate to print the thirteenth character in thethird column, which is the nth column in the example here considered.

Subsequent scan codes will have no effect on the print hammer driver,since they are all discharged. After the sixteenth character pulse, theoutput of the delay line D1 will set the counter to its first state,corresponding to the scan code 1111, in which state it will remain untilthe next print cycle. When the counter shifts to its first state, anoutput pulse is applied from its terminal 1 to terminal a of the hammerdrive control unit 27, to cause it to charge the capacitor in the printhammer driver.

When it is desired to move the paper to the next line position, theswitch 13 is opened. Thus, the apparatus is restored to its initialcondition, except that the data for the line just printed is stillstored in the storage units.

The next index pulse from the generator 4 will switch the flip-flop FFZback to its logical 0 state to cut off the AND gate A2. With theflip-flop FFZ in its logical 0 state, the windings a of the switch coressuch as 8C1 will be unblocked, and the windings b will be blocked. Whenthe first load character pulse is applied to the input terminal m inFIG. 3a, simultaneously with the character code for the last column inthe next line to be printed, it will be gated to the amplifier 4043 topulse the windings (l of all of the switch cores, restoring those whichwere in a logical 1 state to the logical 0 state. In this manner, thedata for the line last printed is erased just before the first charactercode for the next line is stored.

While I have described my invention in terms of the specific details oftwo illustrative embodiments, various changes and modifications will beapparent to those skilled in the art upon reading my description, andsuch can obviously be made without departing from the scope of myinvention.

Having thus described my invention, what I claim is:

1. A code comparator, comprising storage means for storing a firstdigital code sequence having a predetermined number of bits, codegenerating means for generating a series of digital scan code sequencesof said predetermined number of bits and ordered with each sequencecontaining m logical Os preceded by all of the sequences having logical1s in the same positional relationship as the 1's in said digital scancode sequence and at least one additional logical 1, gate meanscontrolled by said storage means for producing an output pulse for eachlogical l in a scan code corresponding to a logical l in the storedcode, a source of sample pulses synchronized with said scan codesequences, and means for producing an output pulse for each sample pulsefor which said gate means produces no output pulse.

2. An ordered sequence comparator, comprising a set of AND gates eachhaving first and second input terminals and an output terminal andproducing an output voltage on said output terminal when and only wheninput voltages are applied to both input terminals, means for applying acode sequence of input voltages to said first terminals of said gates,means for generating a series of scan code sequences of voltages suchthat each sequence containing m logical Us is preceded by all of thesequences having logical 1s in the same positional relationship as thels in said digital scan code sequence and at least one additionallogical 1, means for sequentially applying said series of scan codesequences to the second input terminals of the gates, and circuit meanscontrolled by said gates for producing an output pulse for each scancode sequence for which no gate produces an output pulse.

3. A code comparator, comprising storage means for storing a firstdigital code sequence having a predetermined number of bits, codegenerating means for generating a series of digital scan code sequencesof said predetermined number of bits in an order in which each sequencehaving m Us is preceded by all of the sequences having logical ls in thesame positional relationship as the ls in said digital scan codesequence and at least one more logical 1 which complement the logical lsin a possible stored code sequence, gate means controlled by saidstorage means and said code generating means for producing a pulse foreach logical 1 in a scan code corresponding to a logical 1 in the storedcode, a source of sample pulses synchronized with said scan codesequences, means controlled by said source and said gate means forproducing an output pulse for each Sample pulse for which said gatemeans produces no pulse, and means responsive to the first of saidoutput pulses for producing a command pulse.

4. In combination with a high speed printer of the type in whichprinting means for each column in a line to be printed is successivelyconditioned to print one after another of a predetermined series ofcharacters in a fixed time sequence, means for generating an index pulsebetween the conditioning of the printing means for the last and thefirst character in said sequence, means for :generating a characterpulse corresponding to the conditioning of the printing means for eachcharacter in said sequence, storage means for storing a character indigital code form for each printing means, means for generating a binarysequence of digital code sequences having a bit for each bit of thecharacter codes in which each sequence having in logical Us is precededby all sequences having logical ls in the same positional relationshipas the ls in said digital scan code sequence and at least one morelogical 1, time delay means responsive to said index pulse for applyingsaid character pulses to said counter to step it from one sequence tothe next a predetermined time after the printing means is conditioned ito print each character, a code comparing means for each printing meanscontrolled by said storage means and said counter for producing a pulsefor each counter sequence in which the logical ls are complemented inthe associated character code, and means controlled by each codecomparing means for actuating the associated printing 20 means to printthe character for which it is then conditioned in response to the firstpulse produced by the comparing means.

5. In combination with a high speed printer of the type in whichprinting means for each column in a line to be printed is successivelyconditioned to print one after another of a predetermined series ofcharacters in a fixed time sequence, means for generating an index pulsebetween the conditioning of the printing means for the last and thefirst character in said sequence, means for generating a character pulsecorresponding to the conditioning of the printing means for eachcharacter in said sequence, storage means for storing a character indigital code form for each printing means, a binary counter forgenerating a descending binary sequence of digital code sequences havinga bit for each bit of the character codes, time delay means responsiveto said index pulse for applying said character pulses to said counterto step it from one sequence to the next a predetermined time after theprinting means is conditioned to print each character, a code comparingmeans for each printing means controlled by said storage means and saidcounter for producing a pulse for each counter sequence in which thelogical ls are complemented in the associated character code, and meanscontrolled by each code comparing means for actuating the associatedprinting means to print the character for which it is then conditionedin response to the first pulse produced by the comparing means.

References Cited by the Examiner UNITED STATES PATENTS 2,692,551 10/54Potter 10193 3,054,090 9/62 Link et al. 235-177 3,064,561 11/62 Mauduit10193 3,072,047 1/63 Maudsley et a1. -m 10193 3,103,577 9/ 63 Willard340-1462 X MALCOLM A. MORRISON, Primary Examiner.

ROBERT C. BAILEY, Examiner.

1. A CODE COMPARATOR, COMPRISING STORAGE MEANS FOR STORING A FIRST DIGITAL CODE SEQUENCE HAVING PREDETERMINED NUMBER OF BITS, CODE GENERATING MEANS FOR GENERATING A SERIES OF DIGITAL SCAN CODE SEQUENCES OF SAID PREDETERMINED NUMBER OF BITS AND ORDERED WITH EACH SEQUENCE CONTAINING M LOGICAL O''S PRECEDED BY ALL OF THE SEQUENCES HAVING LOGICAL 1''S IN TEH SAME POSITIONAL RELATIONSHIP AS THE 1''S IN SAID DIGITAL SCAN CODE SEQUENCE AND AT LEAST ONE ADDITIONAL LOGICAL 1, GATE MEANS CONTROLLED BY SAID STORAGE MEANS FOR PRODUCING AN OUTPUT PULSE FOR EACH LOGICAL 1 IN A SCAN CODE CORRESPONDING TO A LOGICAL 1 IN THE STORED CODE, A SOURCE OF SAMPLE PULSES 